and/or/not, nand/nor

 module top;

wire A, B,C,D,A0,B0,C0,D0,out0,out1,out2,out3,F;
system_clock #800 clock0(A);
system_clock #400 clock1(B);
system_clock #200 clock2(C);
system_clock #100 clock3(D);

not a1(A0,A);
not a2(B0,B);
not a3(C0,C);
not a4(D0,D);
and a5(out0,A,C0,D0);
and a6(out1,A0,B0,D);
and a7(out2,B,C0,D0);
and a8(out3,C,D);
or a9(F,out0,out1,out2,out3);

endmodule

module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;

initial clk=0;

always
 begin
#(PERIOD/2) clk=~clk;
 end

always@(posedge clk)
 if($time>1000)$stop;

endmodule

module top;

wire A, B,C,D,A0,B0,C0,D0,F,F1,F2,F3,F4,F5,F6,F7,F8,F9,F10,F11,F12;
system_clock #800 clock0(A);
system_clock #400 clock1(B);
system_clock #200 clock2(C);
system_clock #100 clock3(D);
nand (A0,A,A);
nand (B0,B,B);
nand (C0,C,C);
nand (D0,D,D);
nand na1(F1,A,C0,D0);
nand na2(F2,F1,F1);
nand na3(F3,D,A0,B0);
nand na4(F4,F3,F3);
nand na5(F5,B,C0,D0);
nand na6(F6,F5,F5);
nand na7(F7,C,D);
nand na8(F8,F7,F7);
nand (F9,F2,F2);
nand (F10,F4,F4);
nand (F11,F6,F6);
nand (F12,F8,F8);
nand (F,F9,F10,F11,F12);
endmodule

module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;

initial clk=0;

always
 begin
#(PERIOD/2) clk=~clk;
 end

always@(posedge clk)
 if($time>1000)$stop;

endmodule

3位元全加法器(行為/結構)

 module test_adder1;

 reg [2:0]a,b;
 reg [2:0]carry_in ;
 wire [2:0]sum;
 wire [2:0]carry_out;

 adder1_behavorial A1(carry_out[0], sum[0], a[0], b[0], carry_in[0]);
 adder1_behavorial A2(carry_out[1], sum[1], a[1], b[1], carry_in[1]);
 adder1_behavorial A3(carry_out[2], sum[2], a[2], b[2], carry_in[2]);

 initial
  begin

    carry_in = 0; a = 0; b = 0;
    # 100 if ( carry_out != 0 | sum !== 0)
                $display(" 0+0+0=00 sum is WRONG!");
              else
                $display(" 0+0+0=00 sum is RIGHT!");
    carry_in = 0; a = 0; b = 1;
    # 100 if ( carry_out != 0 | sum !== 1)
               $display(" 0+0+1=01 sum is WRONG!");
              else
               $display(" 0+0+1=01 sum is RIGHT!");
    carry_in = 0; a = 1; b = 0;
    # 100 if ( carry_out != 0 | sum !== 1)
                $display(" 0+1+0=01 sum is WRONG!");
              else
                $display(" 0+1+0=01 sum is RIGHT!");
    carry_in = 0; a = 1; b = 1;
    # 100 if ( carry_out != 1 | sum !== 0)
                $display(" 0+1+1=10 sum is WRONG!");
              else
                $display(" 0+1+1=10 sum is RIGHT!");
    carry_in = 1; a = 0; b = 0;
    # 100 if ( carry_out != 1 | sum !== 0)
                $display(" 1+0+0=01 sum is WRONG!");
              else
                $display(" 1+0+0=01 sum is RIGHT!");
    carry_in = 1; a = 0; b = 1;
    # 100 if ( carry_out != 1 | sum !== 0)
                $display(" 1+0+1=10 sum is WRONG!");
              else
                $display(" 1+0+1=10 sum is RIGHT!");
    carry_in = 1; a = 1; b = 0;
    # 100 if ( carry_out != 1 | sum !== 0)
                $display(" 1+1+0=10 sum is WRONG!");
              else
                $display(" 1+1+0=10 sum is RIGHT!");
    carry_in = 1; a = 1; b = 1;
    # 100 if ( carry_out != 1 | sum !== 1)
               $display(" 1+1+1=11 sum is WRONG!");
              else
               $display(" 1+1+1=11 sum is RIGHT!");
    $finish;
  end
endmodule



module adder1_behavorial (carry_out, sum, a, b, carry_in);
 input a, b, carry_in;
 output carry_out, sum;
  assign sum = (~a&b&~carry_in)|(~carry_in&a&~b)|(a&b&carry_in)|(~a&~b&carry_in);
  assign carry_out = a&carry_in|a&b|b&carry_in;
endmodule

module fulladder (sum, c_out, a, b, c_in);

wire s1, c1, c2;

output sum;

output c_out;

input a, b, c_in;

assign{c_out,sum}=a+b+c_in;

endmodule

module adder3(sum, c_out, a, b, c_in);

wire [2:0] c; 

output [2:0] sum;

output c_out;

input [2:0] a;

input [2:0] b;

input c_in;

fulladder fa1(sum[0], c[1], a[0], b[0], c_in) ;

fulladder fa2(sum[1], c[2], a[1], b[1], c[1]) ;

fulladder fa3(sum[2], c_out, a[2], b[2], c[2]) ;

endmodule

module main;

reg [2:0] a;

reg [2:0] b;

wire [2:0] sum;

wire c_out;

adder3 DUT (sum, c_out, a, b, 1'b0);

initial

begin

  a = 4'b0101;

  b = 4'b0000;

end

always #50 begin

  b=b+1;

  $monitor("%dns monitor: a=%d b=%d sum=%d", $stime, a, b, sum);

end

initial #2000 $finish;

endmodule

11/18 一位元全加法器&行為模式

 module test_adder1;

 reg a,b;
 reg carry_in ;
 wire sum;
 wire carry_out;

 adder1_behavorial A1(carry_out, sum, a, b, carry_in);

 initial
  begin

    carry_in = 0; a = 0; b = 0;
    # 100 if ( carry_out != 0 | sum !== 0)
                $display(" 0+0+0=00 sum is WRONG!");
              else
                $display(" 0+0+0=00 sum is RIGHT!");
    carry_in = 0; a = 0; b = 1;
    # 100 if ( carry_out != 0 | sum !== 1)
               $display(" 0+0+1=01 sum is WRONG!");
              else
               $display(" 0+0+1=01 sum is RIGHT!");
    carry_in = 0; a = 1; b = 0;
    # 100 if ( carry_out != 0 | sum !== 0)
                $display(" 0+1+0=01 sum is WRONG!");
              else
                $display(" 0+1+0=01 sum is RIGHT!");
    carry_in = 0; a = 1; b = 1;
    # 100 if ( carry_out != 0 | sum !== 0)
                $display(" 0+1+1=10 sum is WRONG!");
              else
                $display(" 0+1+1=10 sum is RIGHT!");
    carry_in = 1; a = 0; b = 0;
    # 100 if ( carry_out != 0 | sum !== 0)
                $display(" 1+0+0=01 sum is WRONG!");
              else
                $display(" 1+0+0=01 sum is RIGHT!");
    carry_in = 1; a = 0; b = 1;
    # 100 if ( carry_out != 0 | sum !== 0)
                $display(" 1+0+1=10 sum is WRONG!");
              else
                $display(" 1+0+1=10 sum is RIGHT!");
    carry_in = 1; a = 1; b = 0;
    # 100 if ( carry_out != 0 | sum !== 0)
                $display(" 1+1+0=10 sum is WRONG!");
              else
                $display(" 1+1+0=10 sum is RIGHT!");
    carry_in = 1; a = 1; b = 1;
    # 100 if ( carry_out != 1 | sum !== 1)
               $display(" 1+1+1=11 sum is WRONG!");
              else
               $display(" 1+1+1=11 sum is RIGHT!");
    $finish;
  end
endmodule



module adder1_behavorial (carry_out, sum, a, b, carry_in);
 input a, b, carry_in;
 output carry_out, sum;
  assign sum = (~a&b&~carry_in)|(~carry_in&a&~b)|(a&b&carry_in)|(~a&~b&carry_in);
  assign carry_out = a&carry_in|a&b|b&carry_in;
endmodule

module fulladder (sum , c_out, a , b , c_in);

output sum,c_out;
input a, b, c_in;

wire s1,c1,c2 ;
and(cl, a,b) ;
xor(s1, a,b);
xor  (sum, s1, c_in) ;
and  (c2, s1, c_in) ;
or  (c_out, c2, c1) ;
endmodule

一.二位元多工器(行為模式)

module top;
  integer ia,ib,is;
  reg  a,b,s;
  wire out;

  mux_behavioral mux1(out,a,b,s);

  initial
    begin
      for (is=0; is<=1; is = is+1)
        begin
          s = is;
          for (ia=0; ia<=1; ia = ia + 1)
            begin
              a = ia;
              for (ib=0; ib<=1; ib = ib + 1)
               begin
                 b = ib;
                 #100 $display("a=%d b=%d s=%d   out=%d",a,b,s,out);
               end
            end
        end
    end
endmodule

module mux_behavioral(OUT, A, B, SEL);
 output OUT;
 input A,B,SEL;
 wire  A,B,SEL;
 reg    OUT;

  always @(A or B or SEL)
   OUT = (A & SEL)|(B & ~SEL );
endmodule

module top;  

integer is;

  integer ia[1:0],ib[1:0];

  reg [1:0]a,b;

  reg s;

  wire [1:0]out;

  mux_behavioral mux2(out,a,b,s);

  initial

    begin

      for (is=0; is<=1; is = is + 1)

       begin

        s = is;

         for (ia[0]=0; ia[0]<=1; ia[0] = ia[0]+1)

          begin

           a[0]= ia[0];

            for (ia[1]=0; ia[1]<=1; ia[1] = ia[1]+ 1)

             begin

              a[1] = ia[1];

               for (ib[0]=0; ib[0]<=1; ib[0] = ib[0]+1)

                 begin

                   b[0] = ib[0];

                    for (ib[1]=0; ib[1]<=1; ib[1] = ib[1]+ 1)

                     begin

                      b[1] = ib[1];

                 #1 $display("a[0]=%d a[1]=%d b[0]=%d b[1]=%d s=%d out[0]%d out[1]%d",a[0],a[1],b[0],b[1],s,out[0],out[1]);

                      end

                    end

                  end

              end

         end

    end

endmodule

module mux_behavioral(OUT,A,B,SEL);

 output [1:0]OUT;

 input [1:0] A,B;

 input SEL;

mux1 X1(OUT[0],A[0],B[0],SEL);

mux1 X2(OUT[1],A[1],B[1],SEL);

endmodule

module mux1(OUT, A, B, SEL);

 output OUT;

 input A,B,SEL;

 not n1(NOT_SEL, SEL);

 and a1 (X, A, NOT_SEL);

 and a2 (Y, SEL, B);

 or  o1 (OUT, X, Y);

endmodule

10/28 (1+2)多工器 (2+2)多工器

 module top;

wire [3:0]A,SEL,B,OUT;

system_clock #100 clock1(A[1]);
system_clock #200 clock2(A[0]);
system_clock #6400 clock3(SEL);
system_clock #400 clock4(B[1]);
system_clock #800 clock5(B[0]);
system_clock #1600 clock6(A[2]);
system_clock #3200 clock7(B[2]);
system_clock #800 clock8(A[3]);
system_clock #6400 clock9(B[3]);
mux2 M32(OUT[3:2], A[3:2], B[3:2], SEL);

mux2 M10(OUT[1:0], A[1:0], B[1:0], SEL);

endmodule


module mux2(OUT, A, B, SEL);
output [1:0] OUT;
input [1:0] A,B;
input SEL;
mux hi (OUT[1], A[1], B[1], SEL);
mux lo (OUT[0], A[0], B[0], SEL);
endmodule


module mux(OUT, A, B, SEL);

output OUT;

input A,B,SEL;

not I5 (sel_n, SEL) ;

and I6 (sel_a, A, SEL);

and I7 (sel_b, sel_n, B);

or I4 (OUT, sel_a, sel_b);

endmodule



module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;

initial clk=0;

always
 begin
#(PERIOD/2) clk=~clk;
 end

always@(posedge clk)
 if($time>12800)$stop;

endmodule

mux2 M2(OUT[2], A[2], B[2], SEL);

mux2 M1(OUT[1:0], A[1:0], B[1:0], SEL);

endmodule


module mux2(OUT, A, B, SEL);
output [1:0] OUT;
input [1:0] A,B;
input SEL;
mux hi (OUT[1], A[1], B[1], SEL);
mux lo (OUT[0], A[0], B[0], SEL);
endmodule


module mux(OUT, A, B, SEL);

output OUT;

input A,B,SEL;

not I5 (sel_n, SEL) ;

and I6 (sel_a, A, SEL);

and I7 (sel_b, sel_n, B);

or I4 (OUT, sel_a, sel_b);

endmodule



module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;

initial clk=0;

always
 begin
#(PERIOD/2) clk=~clk;
 end

always@(posedge clk)
 if($time>12800)$stop;

endmodule

10/21

module top;

wire A2,A1,A0,SEL,B2,B1,B0,c0,c1,c2,c3,c4,c5,c6,out7,out8,out9;
system_clock #6400 clock1(SEL);
system_clock #3200 clock2(A2);
system_clock #1600 clock3(A1);
system_clock #800 clock4(A0);
system_clock #400 clock5(B2);
system_clock #200 clock6(B1);
system_clock #100 clock7(B0);

and a0(c0,A2,SEL);
and a1(c1,A1,SEL);
and a2(c2,A0,SEL);

not a5(c5,SEL);

and a3(c3,c5,B2);
and a4(c4,c5,B1);
and a6(c6,c5,B0);
or a7(out7,c1,c4);
or a8(out8,c2,c6);
or a9(out9,c0,c3);
endmodule

module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;

initial clk=0;

always
 begin
#(PERIOD/2) clk=~clk;
 end

always@(posedge clk)
 if($time>6400)$stop;

endmodule

10/14