and/or/not, nand/nor

 module top;

wire A, B,C,D,A0,B0,C0,D0,out0,out1,out2,out3,F;
system_clock #800 clock0(A);
system_clock #400 clock1(B);
system_clock #200 clock2(C);
system_clock #100 clock3(D);

not a1(A0,A);
not a2(B0,B);
not a3(C0,C);
not a4(D0,D);
and a5(out0,A,C0,D0);
and a6(out1,A0,B0,D);
and a7(out2,B,C0,D0);
and a8(out3,C,D);
or a9(F,out0,out1,out2,out3);

endmodule

module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;

initial clk=0;

always
 begin
#(PERIOD/2) clk=~clk;
 end

always@(posedge clk)
 if($time>1000)$stop;

endmodule

module top;

wire A, B,C,D,A0,B0,C0,D0,F,F1,F2,F3,F4,F5,F6,F7,F8,F9,F10,F11,F12;
system_clock #800 clock0(A);
system_clock #400 clock1(B);
system_clock #200 clock2(C);
system_clock #100 clock3(D);
nand (A0,A,A);
nand (B0,B,B);
nand (C0,C,C);
nand (D0,D,D);
nand na1(F1,A,C0,D0);
nand na2(F2,F1,F1);
nand na3(F3,D,A0,B0);
nand na4(F4,F3,F3);
nand na5(F5,B,C0,D0);
nand na6(F6,F5,F5);
nand na7(F7,C,D);
nand na8(F8,F7,F7);
nand (F9,F2,F2);
nand (F10,F4,F4);
nand (F11,F6,F6);
nand (F12,F8,F8);
nand (F,F9,F10,F11,F12);
endmodule

module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;

initial clk=0;

always
 begin
#(PERIOD/2) clk=~clk;
 end

always@(posedge clk)
 if($time>1000)$stop;

endmodule