11/18 一位元全加法器&行為模式

 module test_adder1;

 reg a,b;
 reg carry_in ;
 wire sum;
 wire carry_out;

 adder1_behavorial A1(carry_out, sum, a, b, carry_in);

 initial
  begin

    carry_in = 0; a = 0; b = 0;
    # 100 if ( carry_out != 0 | sum !== 0)
                $display(" 0+0+0=00 sum is WRONG!");
              else
                $display(" 0+0+0=00 sum is RIGHT!");
    carry_in = 0; a = 0; b = 1;
    # 100 if ( carry_out != 0 | sum !== 1)
               $display(" 0+0+1=01 sum is WRONG!");
              else
               $display(" 0+0+1=01 sum is RIGHT!");
    carry_in = 0; a = 1; b = 0;
    # 100 if ( carry_out != 0 | sum !== 0)
                $display(" 0+1+0=01 sum is WRONG!");
              else
                $display(" 0+1+0=01 sum is RIGHT!");
    carry_in = 0; a = 1; b = 1;
    # 100 if ( carry_out != 0 | sum !== 0)
                $display(" 0+1+1=10 sum is WRONG!");
              else
                $display(" 0+1+1=10 sum is RIGHT!");
    carry_in = 1; a = 0; b = 0;
    # 100 if ( carry_out != 0 | sum !== 0)
                $display(" 1+0+0=01 sum is WRONG!");
              else
                $display(" 1+0+0=01 sum is RIGHT!");
    carry_in = 1; a = 0; b = 1;
    # 100 if ( carry_out != 0 | sum !== 0)
                $display(" 1+0+1=10 sum is WRONG!");
              else
                $display(" 1+0+1=10 sum is RIGHT!");
    carry_in = 1; a = 1; b = 0;
    # 100 if ( carry_out != 0 | sum !== 0)
                $display(" 1+1+0=10 sum is WRONG!");
              else
                $display(" 1+1+0=10 sum is RIGHT!");
    carry_in = 1; a = 1; b = 1;
    # 100 if ( carry_out != 1 | sum !== 1)
               $display(" 1+1+1=11 sum is WRONG!");
              else
               $display(" 1+1+1=11 sum is RIGHT!");
    $finish;
  end
endmodule



module adder1_behavorial (carry_out, sum, a, b, carry_in);
 input a, b, carry_in;
 output carry_out, sum;
  assign sum = (~a&b&~carry_in)|(~carry_in&a&~b)|(a&b&carry_in)|(~a&~b&carry_in);
  assign carry_out = a&carry_in|a&b|b&carry_in;
endmodule

module fulladder (sum , c_out, a , b , c_in);

output sum,c_out;
input a, b, c_in;

wire s1,c1,c2 ;
and(cl, a,b) ;
xor(s1, a,b);
xor  (sum, s1, c_in) ;
and  (c2, s1, c_in) ;
or  (c_out, c2, c1) ;
endmodule