integer ia,ib,is;
reg a,b,s;
wire out;
mux_behavioral mux1(out,a,b,s);
initial
begin
for (is=0; is<=1; is = is+1)
begin
s = is;
for (ia=0; ia<=1; ia = ia + 1)
begin
a = ia;
for (ib=0; ib<=1; ib = ib + 1)
begin
b = ib;
#100 $display("a=%d b=%d s=%d out=%d",a,b,s,out);
end
end
end
end
endmodule
module mux_behavioral(OUT, A, B, SEL);
output OUT;
input A,B,SEL;
wire A,B,SEL;
reg OUT;
always @(A or B or SEL)
OUT = (A & SEL)|(B & ~SEL );
endmodule
module top;
integer is;
integer ia[1:0],ib[1:0];
reg [1:0]a,b;
reg s;
wire [1:0]out;
mux_behavioral mux2(out,a,b,s);
initial
begin
for (is=0; is<=1; is = is + 1)
begin
s = is;
for (ia[0]=0; ia[0]<=1; ia[0] = ia[0]+1)
begin
a[0]= ia[0];
for (ia[1]=0; ia[1]<=1; ia[1] = ia[1]+ 1)
begin
a[1] = ia[1];
for (ib[0]=0; ib[0]<=1; ib[0] = ib[0]+1)
begin
b[0] = ib[0];
for (ib[1]=0; ib[1]<=1; ib[1] = ib[1]+ 1)
begin
b[1] = ib[1];
#1 $display("a[0]=%d a[1]=%d b[0]=%d b[1]=%d s=%d out[0]%d out[1]%d",a[0],a[1],b[0],b[1],s,out[0],out[1]);
end
end
end
end
end
end
endmodule
module mux_behavioral(OUT,A,B,SEL);
output [1:0]OUT;
input [1:0] A,B;
input SEL;
mux1 X1(OUT[0],A[0],B[0],SEL);
mux1 X2(OUT[1],A[1],B[1],SEL);
endmodule
module mux1(OUT, A, B, SEL);
output OUT;
input A,B,SEL;
not n1(NOT_SEL, SEL);
and a1 (X, A, NOT_SEL);
and a2 (Y, SEL, B);
or o1 (OUT, X, Y);
endmodule
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