10/21

module top;

wire A2,A1,A0,SEL,B2,B1,B0,c0,c1,c2,c3,c4,c5,c6,out7,out8,out9;
system_clock #6400 clock1(SEL);
system_clock #3200 clock2(A2);
system_clock #1600 clock3(A1);
system_clock #800 clock4(A0);
system_clock #400 clock5(B2);
system_clock #200 clock6(B1);
system_clock #100 clock7(B0);

and a0(c0,A2,SEL);
and a1(c1,A1,SEL);
and a2(c2,A0,SEL);

not a5(c5,SEL);

and a3(c3,c5,B2);
and a4(c4,c5,B1);
and a6(c6,c5,B0);
or a7(out7,c1,c4);
or a8(out8,c2,c6);
or a9(out9,c0,c3);
endmodule

module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;

initial clk=0;

always
 begin
#(PERIOD/2) clk=~clk;
 end

always@(posedge clk)
 if($time>6400)$stop;

endmodule